1) Field of the Invention
This invention relates generally to fabrication of semiconductor devices and more particularly to the fabrication of a MOS transistor using a replacement gate process and where the transistor has low and highxc2x7K gate dielectric layers.
2) Description of the Prior Art
Increasing precision in device manufacturing is required because of the constantly increasing density of semiconductor devices in integrated circuit manufacturing. The ability to control the gate length in field effect transistors (FETs) is of importance. Without the ability to shorten gate length, an increase in density and circuit performance could not be accomplished. Also, because of the reduced gate lengths, there is a need for an improved process that reduces the junction capacitance between the source/drain extension lateral overlap and the gate.
Present gate manufacturing methods result in nonuniform gate length, circuit damage from reactive ion etch (RIE) of the gate lines, and/or require additional processing steps. For example, a substitutional gate method (e.g., replacement gate method) of producing FET gates uses an oxide plug that is created using an anisotropic etch. The oxide plug is then coated with polymer and its surface is planarized. The plug is then removed and substituted by gate metal through lift-off techniques. There are several disadvantages in using the oxide plug method. First, it requires a large increase in photo and process steps. Second, spacers cannot be used in an oxide plug method to reduce gate size. Third, the lift-off technique severely limits the size and thickness of the gate metal line making the process virtually impossible for sub micron gate lengths.
Another method again uses an anisotropic dielectric etch process to control gate length by etching an opening instead of a plug. A dielectric is deposited then the gate opening is anisotropically RIE etched down to the substrate to define gate dimensions. The opening is filled with the gate material and the top surface of the gate line is then patterned with photoresist and etched. Again there are several disadvantages to this method. Since the gate is patterned and etched leaving full thickness on top of the remaining oxide, the planarity of the device is lost, requiring additional dielectric planarization techniques prior to routing interconnect metallization. In addition, spacer technology cannot be used. Without spacer technology, it is difficult to optimize for high device performance without introducing drain induced barrier lowering or device breakdown control problems. This limits the performance and scalability of the device.
A third method for controlling gate length would be a low pressure, high plasma density, RIE etch tool which typically etches material in the five to ten millitorr range. Under these conditions, an anisotropic etch of the gate material can be obtained. Again there are several disadvantages to this method. Damage and contamination from the gate material deposition and etch process can degrade device performance by creating surface states or destroying the crystal structure of the semiconductor. Also, the gate dimension cannot be reduced below the capability of the photoresist alignment tool since sidewall spacers cannot be used to shrink the gate opening beyond its resolution capability.
Because of the reduced gate lengths, there is a need for an improved process that reduces the junction capacitance between the source/drain extension lateral overlap and the gate.
The importance of overcoming the various deficiencies noted above is evidenced by the extensive technological development directed to the subject, as documented by the relevant patent and technical literature. The closest and apparently more relevant technical developments in the patent literature can be gleaned by considering U.S. Pat. No. 6,087,208 (Krivokapic et al.) recites a replacement gate process.
U.S. Pat. No. 6,087,231 (Xiang et al.) shows a replacement gate process with a high-k gate dielectric.
U.S. Pat. No. 6,033,963 (Huang) teaches another replacement gate process.
U.S. Pat. No. 5,447,874 (Grivna) and U.S. Pat. No. 5,966,597 (Wright) show replacement gate processes.
It is an object of the present invention to provide a method for fabricating a MOS transistor using a replacement gate process.
It is an object of the present invention to provide a method for fabricating a field effect transistor (FET) having composite or parallel low and high K gate dielectric layers.
It is an object of the present invention to provide a method for fabricating a field effect transistor (FET) having reduced overlay junction capacitance and form gate dielectric layers containing both low and high K dielectric materials.
It is an object of the present invention to provide a method for fabricating a field effect transistor (FET) having an improved process that reduces the junction capacitance between the source/drain extension lateral overlap and the gate.
To accomplish the above objectives, the present invention provides a method of manufacturing a MOS transistor with an improved junction capacitance. Important elements of the invention are the doped low-k spacers and the high K gate dielectric layer. The low-k spacers and the high K gate dielectric form a portion of the gate dielectric that assist in reducing the junction capacitance between the source/drain extension lateral overlap and the gate.
The invention""s method of fabrication of a transistor comprises following the steps. A dummy gate is formed over a substrate. Ions are implanted into the substrate using the dummy gate as an implant mask to form source and drain regions. A masking layer is formed on the substrate over the source and drain regions and not over the dummy gate. We remove the dummy gate. In a key step, doped low-k spacers are formed an the sidewalls of the masking layer. The doped spacers are heated to diffuse dopant into the substrate to form lightly doped drain (LDD regions). We form a high k (gate) dielectric layer over the masking layer. A gate layer is formed over the high K dielectric layer. The gate layer is chemical-mechanical polishing (CMP) to form a gate over the high k dielectric layer and to remove the gate layer over the masking layer.
The invention""s combination of the low-K spacer and the high K gate dielectric layer reduce junction capacitance between the source/drain extension lateral overlap and the gate because the low k spacer overlies the S/D extension (e.g., LDD). The low k spacer has a lower dielectric constant and thus RC is lowered because Capacitance is lowered. This is important and a benefit because the device has faster signal propagation and larger drive current.
In addition, the invention has the following unique features and benefits:
no spacers surrounding the dummy gate
only a S/D implantxe2x80x94no diffused S/D region
LDD formed from the out diffusion form the doped spacers
a gate dielectric formed from low K and high K materials thus reducing the junction capacitance
tapered gate owing to low-K spacers thus giving a shorter channel length.
The gate channel length can be controlled by changing the size of the doped low-k spacers by changing the anisotropic etch time and anneal time.
Additional objects and advantages of the invention will be set forth in the description that follows, and in part will be obvious from the description, or may be learned by practice of the invention. The objects and advantages of the invention may be realized and obtained by means of instrumentalities and combinations particularly pointed out in the append claims.